OSU CLEO group -- DAQ Project -- The Trigger Interface Module TIM

Front-End Crates

DAQ III Overview

Data-Boards

The CLEO III Trigger Interface Module

The Trigger Interface Module, TIM, receives the event-accept/veto signals from the trigger system and distributes them to the data-board via the crate backplane. It also forms a crate wide busy signal which is used to throttle the CLEO III trigger ( Block Diagram).

Fast Control - Data-Flow Control on the Crate Level

Each front-end crate will be connected to the Data-Flow Control unit (DFC) in the CLEO III trigger system via a dedicated cable. The following signals are carried by the cable. We use differential ECL signals.

L1 , Level 1 accept, from DFC to TIM
Synch, Synchronize, every 256th event, from DFC to TIM
Busy, Crate busy, disable trigger, from TIM to DFC
Error, Crate error, disable trigger, from TIM to DFC
L2strobe, Level 2 decision available, from DFC to TIM
L2data, Level 2 decision, from DFC to TIM

Approximately 2.5 microseconds after an event the trigger system has decided if the detector should be read-out. Data-taking is stopped and a Level 1 trigger signal, L1, is send to the TIM board in each front-end crate. The L1 signal is distributed to the data-boards via the crate backplane (auxiliary backplane in Fastbus, J2 in VME). The data-boards acknowledge by activating their Board_Busy signal. The TIM module forms the logical OR of the Board_Busy signals and the resulting signal, Busy, is send back to the Data-Flow Controller. Once conversion and read-out are complete the data-boards release their individual Board_Busy lines and when the last board is done, TIM de-activates Busy indicating that this crate is ready for the next event. A counter on the TIM module is incremented when Busy is removed to keep track of the number of event fragments waiting in the front-end data-boards. A non-zero value of this counter causes a VME interrupt to the Data-Mover. After the Data-Mover has transferred an event fragment from the data-boards to internal memory, it decrements the fragment counter on the TIM board. The cycle repeats if the counter has not reached zero or when the next event has been stored on the data-boards.

Every 256 events the trigger system sends a Synch pulse together with the regular L1 signal. Logic on the TIM board checks if a synchronization counter shows a multiple of 256, i.e., the lowest 8 bits are cleared. Should synchronization be lost, the crate activates its Error line and the trigger system will initiate a run stop.

Currently no second level trigger is planned for CLEO III but we intend to provide all the required signals and protocols for a future expansion of the system. We distinguish two options: Fast L2 with a Level 2 decision before the data is transferred from the data-boards to the Data-Mover, and Slow L2 with a Level 2 decision before the data is transmitted over the Data-Links to the Event-Builder.

In Fast L2 mode the TIM module delays the Start Read-Out interrupt to the Data-Mover until a Level 2 decision has been received ( L2strobe). For this mechanism to work the L2 signals have to come in sequential order. Both signals, L2strobe and L2data, are stored in a FiFo memory. When the Data-Mover is finally interrupted, it evaluates L2data for this event, that is the next entry in the FiFO, and either commences data-board read-out or starts a flush event procedure. The Busy signal to the trigger system, which determines detector deadtime is de-activated as soon as the data-boards are done and is independent of the Level 2 procedure.

In Slow L2 mode the Data-Mover starts data-board read-out with the removal of Busy as in the original scenario without a second trigger level. However, event data is kept in the Data-Mover until a Level 2 decision is reached. Obviously a larger FiFo is needed in this case. The part of the read-out software on the Data-Mover that is responsible for the data transfer to the event-builder reads the Level 2 information from the TIM module (again, the L2 signals have to come in sequence) and based on L2data skips the event or initiates the transfer.

Implementation

The Trigger Interface Module will be implemented on a standard 6U VME board. The module is designed to operate in both Fastbus and VME front-end crates so a single version can be used for the entire experiment. As indicated in the schematic block diagram several functional units have been combined on the TIM module. These include

Fast Control Interface.
Differential ECL signals are level shifted to TTL. A counter, Trigger, keeps track of the number of L1 trigger signals received. The same counter together with the Synch signal provides a hardware error detection mechanism. A FiFo memory is included should there ever be a need for a second level trigger.
Busy Logic.
The Busy outputs of each data-board are cabled to a front-panel connector on the TIM module where they are are OR-ed to form the crate wide Busy signal. For data-boards without a busy output a common (open collector) Busy line is implemented on the crate backplane. The combined signal, BUSY, increments the Events counter and is fed back to the data-flow controller in the trigger system. The receiver circuit following the front-panel Busy connector automatically adjusts to ECL (Fastbus) or TTL (VME) levels to allow the same TIM module to be used in all CLEO III front-end crates.
VME Interface.
A standard A32/D32 VME slave interface allows the Data-Mover to control the operation of the TIM module. A VME interrupter is included to signal the Data-Mover CPU that event read-out can begin.
A front-panel connector plus interface logic allow timing signals such as Common Stop to be directly connected to the crate backplane.
Trigger Simulator.
A simple trigger simulator is included to allow stand-alone testing without using the CLEO III trigger system. Using a programmable memory look-up table trigger rate and trigger pattern can easily be adjusted over a wide range.

The Fast Control signals arrive at the TIM P2 connector. Hence in VME based systems, the J2 backplane will be used to connect the data-boards with the TIM module. Our solution for Fastbus crates is discussed in the FRITZ page. This approach leaves the J3 backplane in 9U VME crates free for use by the detector components, in particular the trigger system. The selection of pins on the P2 connector will be finalized once the enhanced (5-row) J1/J2 (+J0) backplanes become available.

Front-End Crates DAQ III Overview Data-Boards
CLEO WEB PAGES
Updated: Nov. 15, 1995
Author: Andreas H. Wolf (ahw@mps.ohio-state.edu)